Clock signals are generally required to provide frequency and timing references for controlling internal processes. Recently, clock multiplier circuits have been added on chips to generate an internal clock signal from a reference clock signal. The reference clock signal is typically an external clock signal generated by a crystal oscillator or other external clock source. It may be necessary to generate an internal clock signal having the same frequency or having a frequency that is a fraction or a multiple of the reference clock signal frequency.
When the reference clock signal frequency is an integral multiple (N) of the required internal signal frequency, the internal signal may be generated using a divide-by-N counter that is clocked by the reference signal. When the required signal frequency is an integral multiple of the reference signal frequency, the internal signal may be generated using a phase-locked loop. However, in many applications, the reference signal frequency is a fractional multiple (non-integer) of the required internal signal frequency, where the fractional multiple is either less than or greater than one.
For example, in the field of communications, the required internal signal frequency is often a fractional multiple of the reference clock signal frequency. Generating the desired internal clock signal frequency in such applications while meeting the system requirements has been difficult, costly and/or requires complex hardware.